LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.ALL;
USE WORK.p_alu.ALL;

ENTITY alu2 IS
	PORT ( 	a: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			sel: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
			cin: IN STD_LOGIC;
			y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END alu2 ;

ARCHITECTURE alu2 OF alu2 IS
	signal s_arith: STD_LOGIC_VECTOR(7 DOWNTO 0);
	signal s_logic: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
	U1: logic_unit PORT MAP(a,b,sel,s_arith);
	U2: arith_unit PORT MAP(a,b,sel,cin,s_logic);
	U3: mux PORT MAP(s_arith,s_logic,sel(3),y);
END alu2;